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per pin parametric measurement unit/source measure unit ad5520 rev. b information furnished by analog devices is believed to be accurate and reliable. however, no responsibility is assumed by analog devices for its use, nor for any infringements of patents or other rights of third parties that may result from its use. specifications subject to change without notice. no license is granted by implication or otherwise under any patent or patent rights of analog devices. trademarks and registered trademarks are the property of their respective owners. one technology way, p.o. box 9106, norwood, ma 02062-9106, u.s.a. tel: 781.329.4700 www.analog.com fax: 781.461.3113 ? 2005 analog devices, inc. all rights reserved. features force/measure functions fimv, fvmi, fvmv, fimi, fnmv force/measure voltage range 11 v 4 user programmable force/measure current ranges 4 a, 40 a, 400 a, 4 ma (external resistors) 2 user programmable extended current ranges up to 6 ma without external driver higher currents with external driver clamp circuitry and window comparators on board guard amplifier 64-lead lqfp package applications automatic test equipment per pin pmu, shared pin pmu, device power supply instrumentation source measure, parametric measurement, precision measurement general description the ad5520 is a single-channel, per pin parametric measure- ment unit (ppmu) for use in semiconductor automatic test equipment. the part is also suited for use as a source measurement unit for instrumentation applications. it contains programmable modes to force a pin voltage and measure the corresponding current, or force a current and measure the voltage. the ad5520 can force/measure over a 11 v range or user-programmable currents up to 4 ma with its on-board force amplifier. an external amplifier is required for wider current ranges. the device provides a force sense capability to ensure accuracy at the tester pin. a guard output is also available to drive the shield of a force/sense pair. the ad5520 is available in a 64-lead lqfp package. functional block diagram clldetect measi4h fin bw select compout2 foh1 foh2 foh3 foh0 av ee av cc clh cll refgnd measiout measout measvout g = 16 g = 1 cph cpoh cpol cpl measi5h measil guardin guard measvh measvl agnd qm5 qm4 dgnd dv dd cs standby compout1 compout0 compin2 compin1 compin0 clamp detect i sense inst amp v sense inst amp logics ac0 ac1 clhdetect moe am0 am1 am2 msel fsel cpsel stb cpck ad5520 comparator g = 1 foh measi3h measi2h measi1h measi0h 03701-001 figure 1.
ad5520 rev. b | page 2 of 24 table of contents features .............................................................................................. 1 applications ....................................................................................... 1 general description ......................................................................... 1 functional block diagram .............................................................. 1 specifications ..................................................................................... 3 timing characteristics ..................................................................... 6 absolute maximum ratings ............................................................ 7 esd caution .................................................................................. 7 pin configuration and function descriptions ............................. 8 typical performance characteristics ........................................... 10 theory of operation ...................................................................... 13 interface ........................................................................................... 14 standby mode ............................................................................. 14 force voltage or force current ................................................ 14 measured parameter .................................................................. 14 current ranges ........................................................................... 14 r s selection .................................................................................. 14 force control amplifier ............................................................ 15 comparator function and strobing ........................................ 15 clamp function .......................................................................... 15 high current ranges ................................................................. 15 circuit operation ........................................................................... 16 force voltage ............................................................................... 16 measure current ......................................................................... 16 force current .............................................................................. 17 measure voltage ......................................................................... 17 short circuit protection ............................................................ 17 settling time considerations ....................................................... 18 pcb layout and power supply decoupling ................................ 19 typical connection circuit for the ad5520 .............................. 20 typical application circuit ........................................................... 21 evaluation board for the ad5520 ................................................ 22 outline dimensions ....................................................................... 24 ordering guide .......................................................................... 24 revision history 9/05rev. a to rev. b updated format..................................................................universal changes to features.......................................................................... 1 changes to figure 1.......................................................................... 1 changes to specifications ................................................................ 3 changes to force current section................................................ 17 changes to figure 26 ..................................................................... 20 updated outline dimensions ....................................................... 24 changes to ordering guide .......................................................... 24 10/03rev. 0 to rev. a changes to specifications.................................................................3 updated ordering guide .................................................................5 9/03revision 0: initial version
ad5520 rev. b | page 3 of 24 specifications av cc = +15 v 5%, av ee = ?15 v 5%, dv dd = 5 v 10%, agnd = 0 v, refgnd = 0 v, dgnd = 0 v. all specifications 0c to 70c, unless otherwise noted. table 1. parameter min typ 1 max unit test conditions/comments voltage force mode force control output voltage range 11 v r load = 10 k, c load = 50 pf foh output impedance 70 foh0 2.5 k foh1 3 k foh2 500 foh3 60 input offset error 1 5 mv input offset error temperature coefficient 10 v/c gain error 1 % clamp current error 2 1 % fs of fin current measure/force suggested va lues; set with extern al sense resistors foh0 4 a mode0, r s = 125 k foh1 40 a mode1, r s = 12.5 k foh2 400 a mode2, r s = 12.5 k foh3 4 ma mode3, r s = 125 current measure mode high sense input range, v measixh 11 v linearity 3 0.01 % fsr +11 v > v fol > ?11 v input bias current 1 3 na input bias current drift 1 50 pa/c output offset error 100 mv mode0 (4 a) 100 mv mode1 (40 a) 100 mv mode2 (400 a) 100 mv mode3 (4 ma) output offset error temperature coefficient 10 v/c gain error 0.1 0.35 % gain of 16 gain error temperature coefficient 4 30 ppm/c measiout output load current 4 ma cmrr 95 db @ dc current force mode input offset error 10 mv with mode0, mode1, mode2, mode3 gain error 1 % clamp voltage error 2 1 % fs of fin voltage measure mode differential input range 11 v low sense input voltage range 100 mv measvl linearity 3 +0.005 % fsr +11 v > v measvh to v measvl > ?11 v input offset error 5 10 mv fin = 0 v, measured @ measvout input offset error temperature coefficient 1 15 v/c gain error 0.03 0.15 % gain of 1 gain error temperature coefficient 4 2 ppm/c input bias current 1 3 na input bias current drift 4 50 pa/c measvout output load current 4 ma cmrr 4 73 db @ dc
ad5520 rev. b | page 4 of 24 parameter min typ 1 max unit test conditions/comments amplifier settling time 4 , 5 v sense amp 20 s to 0.2% i sense amp 12 s to 0.2% loop settling 4 , 5 settling to within 0.024% of 8 v step compin2 = 100 pf 450 600 s mode0 285 390 s mode1 170 240 s mode2, mode3 compin1 = 1000 pf 2 2.5 ms mode0 1.8 2.4 ms mode1, mode2, mode3 compin0 = 3000 pf 5.75 8.7 ms mode0, mode1, mode2, mode3 slew rate 4 , 5 50 mv/s compin2 = 100 pf 4.3 mv/s compin1 = 1000 pf 1.28 mv/s compin0 = 3000 pf comparator cph, cpl input range 11 v v cph > v cpl input offset 7 mv guard driver output voltage 11 v output impedance 130 capacitive load only output offset voltage 400 mv load current 4 4 ma output settling time 4 0.5 2 s 100 pf capacitive load analog reference inputs force control input range 11 v force control input impedance 1 m clamp control input range 11 v v clh > v cll clamp control input impedance 1 m comparator threshold input range 11 v comparator threshold input impedance 1 m input capacitance 4 3 pf leakage current measixx, measvx, measout leakage 3 20 na analog measurement outputs voltage measure output impedance 2 current measure output impedance 3 multiplexed sense output impedance 1 k input capacitance measixh, measvh, fohx 8 pf logic inputs input current 1 a all digital inputs together input low voltage, v inl 0.8 v input high voltage, v ihl 2.0 v input capacitance 4 3 pf logic outputs output low voltage, v ol 4 0.4 v i sink = 2 ma output high voltage, v oh 4 2.4 v i source = 2 ma
ad5520 rev. b | page 5 of 24 parameter min typ 1 max unit test conditions/comments power requirements av cc 14.25 15 15.75 v for specific performance 6 av ee ?14.25 ?15 +15.75 v power supply rejection ratio, psrr 1 foh ?25 db 100 khz ?16 db 500 khz ?15 db 1 mhz measout ?55 db 100 khz ?10 db 500 khz dc psr 90 db dv dd 5 v i avcc 12 ma i avee 12 ma i dvdd 0.5 ma digital inputs at supply rails 1 typical values are at 25c and nominal supply, unless otherwise noted. 2 full-scale = 11 v. 3 full-scale range = 22 v. 4 guaranteed by design and characterizati on, but not subject to production test. 5 force control amplifier dominates slew rate and settling time. 6 operational with 12 v supplies, force/measure range is reduced to 8.5 v.
ad5520 rev. b | page 6 of 24 timing characteristics av cc = +15 v 5%, av ee = ?15 v 5%, agnd = 0 v, refgnd = 0 v, dgnd = 0 v. all specifications 0c to 70c, unless otherwise noted. 1 , 2 table 2. dv dd parameter 5 v 10% 3.3 v unit conditions/comments t 1 0 0 ns min cs falling edge to stb falling edge setup time t 2 30 200 ns min stb pulse width t 3 40 70 ns min stb rising edge to cs rising edge setup time t 4 0 40 ns min data setup time t 5 550 560 ns min cs falling edge to cpck rising edge setup time t 6 320 320 ns min cpck pulse width t 7 450 500 ns min cpck to stb falling edge setup time t 8 150 800 ns min stb rising edge to qmx, clxdetect valid t 9 100 440 ns min stb rising edge to cpoh, cpol valid t 10 240 240 s min comparator setup time, mode2, mode3 settling t 11 150 500 ns min comparator hold time t 12 100 440 ns min comparator output delay time t 13 320 320 ns min comparator strobe pulse width 1 see figure 2. 2 all input signals are specified with tr = tf = 1 ns (10% to 90% of v dd ) and timed from a voltage level of (v il + v ih )/2. cpck amx, acx, fsel, msel, cpsel cs qm4, qm5, clhdetect, clldetect cpol, cpoh stb t 2 t 1 t 3 t 6 t 5 t 7 t 4 t 6 t 9 03701-002 figure 2. timing diagram cpck cpoh, cpol measvout or measiout t 11 t 12 t 10 t 13 03701-003 figure 3. comparator timing
ad5520 rev. b | page 7 of 24 absolute maximum ratings t a = 25c, unless otherwise noted. table 3. parameter rating av cc to av ee 34 v av cc to agnd ?0.3 v, +17 v av ee to agnd +0.3 v, ?17 v dv dd ?0.3 v to +6 v digital inputs to dgnd ?0.3 v to dv dd + 0.3 v analog inputs to agnd av cc + 0.3 v to av ee C 0.3 v clh to cll ?0.3 v to +34 v cph to cpl ?0.3 v to +34 v refgnd, dgnd av cc + 0.3 v to av ee C 0.3 v operating temperature range commercial (j version) 0 c to 70 c storage temperature range ?65 c to +150 c maximum junction temperature, (t j max) 150 c package power dissipation (t j max C t a )/ ja thermal impedance ja 47.8 c /w lead temperature (soldering 10 sec) 300 c ir reflow, peak temperature 220 c stresses above those listed under absolute maximum ratings may cause permanent damage to the device. this is a stress rating only; functional operation of the device at these or any other conditions above those indicated in the operational section of this specification is not implied. exposure to absolute maximum rating conditions for extended periods may affect device reliability. esd caution esd (electrostatic discharge) sensitive device. electros tatic charges as high as 4000 v readily accumulate on the human body and test equipment and can discharge wi thout detection. although this product features proprietary esd protection circuitry, permanent dama ge may occur on devices subjected to high energy electrostatic discharges. therefore, proper esd precautions are recommended to avoid performance degradation or loss of functionality.
ad5520 rev. b | page 8 of 24 pin configuration and fu nction descriptions 64 cll 63 clh 62 fin 61 measvout 60 measiout 59 refgnd 58 measout 57 refgnd 56 compin2 55 compin1 54 compin0 53 compout2 52 compout1 51 compout0 50 av cc_b 49 foh 47 measi5h 46 measi4h 45 foh3 42 measi2h 43 foh2 44 measi3h 48 av ee_b 41 foh1 40 measi1h 39 foh0 37 measil 36 measvh 35 guard(nc) 34 measvl 33 av cc_g 38 measi0h 2 cpl 3 dv dd 4 cpoh 7 dgnd 6 cpck 5 cpol 1 cph 8 clhdetect 9 clldetect 10 qm4 12 moe 13 cs 14 stb 15 ac0 16 ac1 11 qm5 nc = no connect 17 dgnd 18 dv dd 19 am2 20 am1 21 am0 22 standby 23 fsel 24 msel 25 cpsel 26 av ee 27 av cc 28 agnd 29 av ee_g 30 guard 31 nc 32 guardin pin 1 ad5520 top view (not to scale) 03701-004 figure 4. pin configuration table 4. pin function descriptions pin no. mnemonic description 1 cph upper comparator threshold voltage input, cph > cpl. 2 cpl lower comparator threshold voltage input, cpl < cph. 3, 18 dv dd digital supply voltage. 4 cpoh logic output. when high, indicates measvout or measiout > cph. 5 cpol logic output. when high, indicates measvout or measiout < cpl. 6 cpck logic input. used to initiate comp arator sampling and update cpoh and cpol. 7, 17 dgnd digital ground. 8 clhdetect logic output. when high, indicates upper clamp active. see the clamp function section. 9 clldetect logic output. when high, indicates lower clamp active. see the clamp function section. 10 qm4 logic output. when high, indicates current range mode 4 is enabled. may be used to drive external relay or switch. see the high current ranges section. 11 qm5 logic output. when high, indicates current range mode 5 is enabled. may be used to drive external relay or switch. see the high current ranges section. 12 moe active low measout enable. 13 cs active low logic input. the device is selected when this pin is low. see the interface section. 14 stb active low logic input. used in conjunction with cpck and cs to configure the device for different configurations. rising edge of stb triggers sequence inputs. see the interface section. 15 ac0 logic input. used in conjunction with ac1 to sele ct one of three external compensation capacitors. see the force control amplifier section. 16 ac1 logic input. used in conjunction with ac0 to sele ct one of three external compensation capacitors. see the force control amplifier section. 19 am2 logic input. used in conjunction with am1 and am0 to select one of six current ranges or to enable standby mode. see the current ranges section. 20 am1 logic input. used in conjunction with am2 and am0 to select one of six current ranges or to enable standby mode. see the current ranges section. 21 am0 logic input. used in conjunction with am2 and am1 to select one of six current ranges or to enable standby mode. see the current ranges section. 22 standby logic input. when high, device is in standby mode of operation. see the standby mode section.
ad5520 rev. b | page 9 of 24 pin no. mnemonic description 23 fsel logic input. force mode select. used to select between current or voltage force operation. see the force voltage or force current section. 24 msel logic input. measure mode select. used to connect m easout to either measiout when high or measvout when low. 25 cpsel logic input. comparator select. used to compare cpl, cph to measvout when low, or to measiout when high. see the comparator function and strobing section. 26 av ee most negative supply voltage. 27 av cc most positive supply voltage. 28 agnd measx input ground. 29 av ee_g most negative supply voltage. 30 guard guard output. 31 nc no connect. 32 guardin guard input. 33 av cc_g most positive supply voltage. 34 measvl dut voltage sense inputs (low sense). 35 guard(nc) no connect. 36 measvh dut voltage sense inputs (high sense). 37 measil dut current sense inputs (low sense). 38 measi0h dut current sense inputs (high sense). 39 foh0 force control voltage output. 40 measi1h dut current sense inputs (high sense). 41 foh1 force control voltage output. 42 measi2h dut current sense inputs (high sense). 43 foh2 force control voltage output. 44 measi3h dut current sense inputs (high sense). 45 foh3 force control voltage output. 46 measi4h dut current sense inputs (high sense). 47 measi5h dut current sense inputs (high sense). 48 av ee_b most negative supply voltage. 49 foh external force driver control voltage output. 50 av cc_b most positive supply voltage. 51 compout0 compensation capacitor 0 output. 52 compout1 compensation capacitor 1 output. 53 compout2 compensation capacitor 2 output. 54 compin0 compensation capacitor 0 input. 55 compin1 compensation capacitor 1 input. 56 compin2 compensation capacitor 2 input. 57, 59 refgnd analog input/output reference ground. 58 measout multiplexed dut voltage/current sense output. see the measured parameter section. 60 measiout dut current sense output. 61 measvout dut voltage sense output. 62 fin force control voltage input. 63 clh upper clamp voltage input clh > cll. 64 cll lower clamp voltage cll < clh.
ad5520 rev. b | page 10 of 24 typical performance characteristics v dd = +15v v ss = ?15v mode 3 temperature ( c) vm linearity (%) 0.0030 0.0005 0.0010 0.0015 0.0020 0.0025 0 0 10203040506070 03701-005 figure 5. voltage sense amplifier linearity vs. temperature v dd = +15v v ss = ?15v t a = 25 c frequency (hz) amplitude (db) 80 10 20 30 50 60 40 70 0 1 10 100 1k 10k 100k 1m 03701-006 figure 6. voltage sense amplifier cmrr vs. frequency v dd = +15v v ss = ?15v t a = 25 c c comp = 0.1nf c comp = 3.3nf c comp = 1.0nf frequency (hz) amplitude (db) 10 ?50 ?30 ?20 ?10 0 ?40 ?60 100 1k 10k 100k 03701-007 figure 7. force amplifier bandwidth, mode 0 (4 a) v dd = +15v v ss = ?15v mode 3 temperature ( c) im linearity (%) 0.0030 0.0005 0.0010 0.0015 0.0020 0.0025 0 0 10203040506070 03701-008 figure 8. current sense linearity vs. temperature v dd = +15v v ss = ?15v t a = 25 c i sense cmrr frequency (hz) cmrr (db) 140 20 60 80 100 120 40 0 1 10 100 1k 10k 100k 1m 03701-009 figure 9. current sense amplifier cmrr vs. frequency v dd = +15v v ss = ?15v t a = 25 c c comp = 0.1nf c comp = 3.3nf c comp = 1.0nf frequency (hz) amplitude (db) 5 ?35 ?25 ?20 ?15 ?10 ?5 0 ?30 ?40 100 1k 10k 100k 03701-010 figure 10. force amplifier bandwidth, mode 1 (40 a)
ad5520 rev. b | page 11 of 24 v dd = +15v v ss = ?15v t a = 25 c c comp = 0.1nf c comp = 3.3nf c comp = 1.0nf frequency (hz) amplitude (db) ?35 ?25 ?20 ?15 ?10 ?5 0 ?30 ?45 ?40 100 1k 10k 100k 03701-011 figure 11. force amplifier bandwidth, mode 2 (400 a) v dd = +15v v ss = ?15v t a = 25 c frequency (hz) amplitude (db) 5 ?35 ?25 ?20 ?15 ?10 ?5 0 ?30 ?40 11 k 100 10 1m 100k 10k 10m 100m 03701-012 figure 12. guard amplifier bandwidth v dd = +15v v ss = ?15v t a = 25 c frequency (hz) amplitude (db) 20 ?50 ?40 ?30 ?20 ?10 0 10 ?60 100k 1m 10m 03701-013 figure 13. current sense amplifier ac psrr v dd = +15v v ss = ?15v t a = 25 c c comp = 0.1nf c comp = 3.3nf c comp = 1.0nf frequency (hz) amplitude (db) ?35 ?25 ?20 ?15 ?10 ?5 0 ?30 ?45 ?40 100 1k 10k 100k 03701-014 figure 14. force amplifier bandwidth, mode 3 (4 ma) v dd = +15v v ss = ?15v t a = 25 c frequency (hz) amplitude (db) 30 ?20 0 ?10 10 20 ?30 100 1k 1m 100k 10k 10m 03701-015 v sense i sense figure 15. voltage sense and curre nt sense amplif ier bandwidths frequency (hz) amplitude (db) 0 ?25 ?20 ?10 ?30 ?15 ?5 100k 1m 10m 03701-016 v dd = +15v v ss = ?15v t a = 25 c figure 16. force amplifier ac psrr, mode 3, c comp = 100 pf
ad5520 rev. b | page 12 of 24 frequency (hz) amplitude (db) 20 10 0 ?50 ?40 ?20 ?60 ?30 ?10 100k 1m 10m 03701-017 v dd = +15v v ss = ?15v t a = 25 c figure 17. voltage sense amplifier ac psrr frequency (hz) nv/ hz 700 100 300 200 400 500 600 0 10 100 10k 1k 100k 03701-018 i sense v sense foh guard figure 18. noise spectral density time (ms) voltage (v) 16 0 6 8 4 2 10 12 14 ?2 05 35 25 30 10 15 20 4540 03701-019 v cc v dut figure 19. power up time (s) voltage (v) 9 0 3 4 2 1 5 6 7 8 ?1 0 0.006 0.004 0.005 0.001 0.002 0.003 0.008 0.007 03701-020 compin2 = 100pf compin1 = 1000pf compin2 = 3000pf figure 20. settling time, mode 2
ad5520 rev. b | page 13 of 24 theory of operation the ad5520 is a single-channel per pin parametric measure- ment unit (ppmu) for use in semiconductor automatic test equipment. it contains programmable modes to force a pin voltage and measure the corresponding current (fvmi), force current measure voltage (fimv), force current measure current (fimi), force voltage measure voltage (fvmv), and force nothing measure voltage (fnmv). the ppmu can force or measure a voltage from ?11 v to +11 v. it can force or measure currents up to 6 ma using the internal amplifier, while the addition of an external amplifier enables higher current ranges. external resistors allow users to choose the optimum ranges for their needs. the device provides a force sense capability to ensure accuracy at the tester pin. a guard output is also available to drive the shield of a force/sense pair. the ad5520 has an on-board window comparator that provides two bits of useful information, dut too low or too high. also provided on the chip is clamp circuitry that flags via clhdetect and clldetect if the voltage applied to fin or across the dut exceeds the voltage applied to cll and clh. on-chip is clamp circuitry that clamps the output of the force amplifier if the voltage at measiout and measvout exceeds cll or clh.
ad5520 rev. b | page 14 of 24 interface the ad5520 ppmu is controlled via a number of digital inputs, which are discussed in detail in the following sections. all inputs are ttl-compatible. cs is used to select the device while stb (active low input) latches data available on the other digital inputs and updates any required digital outputs. the rising edge of stb triggers sequence inputs. the remaining digital inputs control the function of the pmu. they also determine which measure mode the pmu is in, the compensation capacitor used, and the selected current range. standby mode the ad5520 can be placed into standby mode via the standby logic input. in this mode, the force amplifier is disconnected from the force input (fin). in addition, the switch in series with the force output pins (fohx) is opened, and the current measure amplifier is disconnected from the sense resistors. the voltage measure amplifier is still connected across the dut; therefore, dut voltage measurements may still be made while in standby mode. figure 21 shows the configuration of the pmu while in standby mode. table 5. standby mode standby function low normal force mode high standby mode dac measihx measil measvh measvl fohx r s dut fin measiout measvout g = 16 g = 1 03701-021 figure 21. pmu in standby mode force voltage or force current fsel is an input that determines whether the ppmu forces a voltage or current. table 6. fsel function fsel function low voltage force and current clamp with measiout voltage high current force and voltage clamp with measvout voltage measured parameter measout is a muxed output that tracks the sensed parameter. msel (digital input) connects the measout to the output of the current sense amplifier or the voltage sense amplifier, depending on which is the measured parameter of interest. the measout pin is connected back to an adc to allow the measured value to be converted to a digital code. table 7. measout connected to voltage or current msel function low measout = dut voltage high measout = dut current the measout pin can also be made high impedance through the moeb logic input. table 8. moeb allows measout to go high impedance moeb function low enable measout output high hi-z measout output current ranges a number of current ranges are possible with the ad5520. the am0, am1, and am2 pins are digital inputs used to establish full-scale current range of the pmu. table 9. selection of current range am0 am1 am2 function low low low current range mode0 (4 a) high low low current range mode1 (40 a) low high low current range mode2 (400 a) high high low current range mode3 (4 ma) low low high current range mode4 (external buffer mode) high low high current range mode5 (external buffer mode) low high high standby (same as standby = high) high high high standby (same as standby = high) r s selection the ad5520 is designed to ensure the voltage drop across each of the r s resistors is less than 500 mv when maximum current is flowing through them. to support other current ranges, these sense resistor values can be changed. the force amplifier can drive a maximum of 6 ma. it is not recommended to increase the maximum current above the nominal range. the two external current ranges use an external buffer to drive higher current. the example in figure 26 uses 40 ma and 160 ma ranges. these ranges can be changed to suit user requirements for a high current range.
ad5520 rev. b | page 15 of 24 force control amplifier the force control amplifier requires external capacitors connected between the compoutx and compinx pins. for stability with large capacitance at the dut, the largest capacitance value (3000 pf) should be selected. the force control amplifier should always contribute the dominant pole in the control loop. settling times increase with larger capacitances. acx inputs select which external compensation capacitor is used. table 10. ac0, ac1 compensation capacitor selection ac0 ac1 function low low select external compensation capacitor 0 high low select external compensation capacitor 1 low high select external compensation capacitor 2 comparator function and strobing the ad5520 has an on-board window comparator that provides two bits of useful information, dut too low or dut too high. cpsel is the digital input that controls this function, selecting whether it should compare to the voltage sense or the current sense amplifier. table 11. comparator function select cpsel function low compare cpl, cph to measvout high compare cpl, cph to measiout after cpsel has selected which amplifier output is of interest, logic input cpck is used to initiate comparator sampling and update the logic outputs cpoh and cpol. this indicates whether the voltages at measiout or measvout have exceeded voltages set at cpl or cph (thus providing dut too high or dut too low information). a rising edge on stb is required to clock the cpoh and cpol data out. table 12. cpck synchronous logic outputs cpoh function low high measvout or measiout < cph measvout or measiout > cph cpol function low high measvout or measiout > cpl measvout or measiout < cpl clamp function clamp circuitry, which is also included on-chip, clamps the force amplifiers output if the voltage or current applied to the dut exceeds the clamp levels, cll and clh. the clamp circuitry also comes into play in the event of a short or open circuit. when in force current range, the voltage clamps protect the dut from an open circuit. likewise, when forcing a voltage and a short circuit occurs, the current clamps protect the dut. the clamps also function to protect the dut if a transient voltage or current spike occurs when changing to a different operating mode, or when programming the device to a different current range. the digital output flags, which indicate a clamp limit has been hit, are clhdetect for the upper clamp, and clldetect output for the lower clamp. table 13. clamp detect outputs clhdetect function low upper clamp inactive high upper clamp active clldetect function low lower clamp inactive high lower clamp active high current ranges with the use of an external high current amplifier, two high current ranges are possible. the current range values can be set as required in the application through appropriate selection of the sense resistors connected between measi5h, measi4h, and measil. when one of these high current ranges (mode 4 or mode 5) is selected via the amx control lines, the appro- priate qm4 or qm5 output is enabled. as a result, these outputs can be used to control relays connected in series with the high current amplifier, as shown in figure 26 . table 14. high current range logic outputs qm4 qm5 function high low current range mode 4 enable output low high current range mode 5 enable output
ad5520 rev. b | page 16 of 24 circuit operation force voltage most pmu measurements are performed while in force voltage and measure current modes; for example, when the device is used as a device power supply, or in continuity or leakage testing. in the force voltage mode, the voltage at analog input fin is mapped directly to the voltage forced at the dut. when in force voltage and measure current modes, the maximum voltage applied to the input corresponds to the maximum current outputs. figure 22 shows the transfer function when forcing a voltage. v dut v cll r s 16 r dut v clh r s 16 r dut r s 16 v clh r s 16 v cll v clh v clh i dut v fin v fin 03701-022 figure 22. force voltage transfer function measure current figure 23 shows a simplified diagram of the pmu when in force voltage mode. the control loop consists of the force amplifier with the voltage sense amplifier making up the feedback path. current flowing through the dut is measured by sensing the current flowing through a selectable sense resistor, which is in series with the dut. the current sense amplifier (gain = 16) generates a voltage at its output, which is proportional to the current flowing through the dut. this voltage is compared to the cll and clh levels to ensure the clamp voltages have not been exceeded. strobing cpck and stb provides information about the voltage level with respect to the comparator levels, cph and cpl. measihx measil g=16 measvh measvl g = 1 fohx r s r dut fin vmeasiout vmeasvout measiout measvout clh cll vcll vclh vfin condition output v clh > i dut r s 16 v cll < i dut r s 16 v dut = v fin v dut = v clh v dut = v cll v clh > i dut r s 16 v cll > i dut r s 16 v clh < i dut r s 16 v cll < i dut r s 16 refgndi/v v v 03701-023 figure 23. force voltage, measure current mode
ad5520 rev. b | page 17 of 24 force current in force current mode, the voltage at fin is now converted to a current through the following relationship: force current = v fin /(r sense 16) figure 24 shows a simplified diagram of the pmu when in force current mode. the control loop consists of the force amplifier with the current sense amplifier making up the feedback path. in this case, voltage at the dut is sensed across the voltage measure amplifier (gain = 1) and presented at the measvout output. measihx measil g=16 measvh measvl g = 1 fohx r s r dut fin vmeasiout vmeasvout measiout measvout clh cll vcll vclh vfin condition output v clh > v dut v cll < v dut v clh > v dut v cll > v dut v clh < v dut v cll < v dut refgndi/v v v 03701-024 i dut = r s v fin i dut = r s v clh i dut = r s v cll figure 24. current force, voltage measure mode measure voltage a dut voltage is tested via the voltage measure amplifier by a window comparator to ensure that cph and cpl levels are not exceeded. in addition, the dut voltage is automatically tested against the voltage levels at the clamp, and clamp flags are enabled if the dut voltage exceeds either of the levels. short circuit protection the ad5520 is designed to withstand a direct short circuit on any of the amplifier outputs. figure 25 illustrates the transfer function of the current force mode. i dut r dut v cll r dut v clh v clh v clh v clh v clh v dut v fin v fin 03701-025 figure 25. current force transfer function
ad5520 rev. b | page 18 of 24 settling time considerations fast throughput is a key requirement in automatic test equipment because it relates directly to the cost of manufac- turing the dut; thus reducing the time required to make a measurement is of greatest importance. when taking measurements using a pmu, the limiting factor is usually the time it takes the output to settle to the required accuracy so a measurement can be taken. dut capacitance, measurement accuracy, and the design of the pmu are the major contributors to this time. figure 26 shows a simplified block diagram of the ad5520 pmu. in brief, the device consists of a force control amplifier, access to a number of selectable sense resistors, a voltage measure instrumentation amplifier, and a current measure instrumentation amplifier. to optimize the performance of the device, there are also nodes provided where external compensa- tion capacitors are added. as mentioned, making an accurate measurement in the fastest time while avoiding overshoots and ringing is the key requirement in any automatic test equipment (ate) system. doing so provides challenges, however. the external compensation capacitors set up different settling times or bandwidths on the force control amplifier, and while one compensation capacitor value may suit one range, it may not suit other ranges. to optimize measurement performance and speed, differences in signal behavior on each range and frequency of use of each range need to be taken into account. when selecting a faster settling time, there is a trade-off. a small compensation value results in faster settling, but may incur penalties in overshoots or ringing at the dut. compensation capacitor selection should be optimized to ensure minimum overshoots while still giving decent settling time performance. while careful selection of the compensation capacitor is required to minimize the settling time, another factor can greatly contribute to the overall settling of the loop if the feedback loop is broken in some manner, and the force control amplifier goes to either the positive or negative rails. there is a finite amount of time required for the amplifier to recover from this condition, typically 85 s, which adds to the settling of the loop. ensuring that the force control amplifier never goes into saturation is the best solution. this solution can be helped by putting the device into standby mode any time the operating mode or range selection is changed. in addition, ensure that the selected output range can supply the required current needed by the dut.
ad5520 rev. b | page 19 of 24 pcb layout and power supply decoupling in any circuit where accuracy is important, careful considera- tion to the power supply and the ground return layout helps to ensure the rated performance. the printed circuit board on which the ad5520 is mounted should be designed so that the analog and digital sections are separated and confined to certain areas of the board. if the pmu is in a system where multiple devices require an agnd-to-dgnd connection, the connection should be made at one point only. the star ground point should be established as close as possible to the device. this pmu should have ample supply bypassing of 10 f in parallel with 0.1 f on the supply and should be located as close as possible to the package, ideally right up against the device. the 0.1 f capacitor should have low effective series resistance (esr) and effective series inductance (esi), such as the common ceramic types that provide a low impedance path to ground at high frequencies, to handle transient currents due to internal logic switching. low esr (1 f to 10 f) tantalum or electrolytic capacitors should also be applied at the supplies to minimize transient disturbance and filter out low frequency ripple. fast switching signals, such as clocks, should be shielded with digital ground to avoid radiating noise to other parts of the board and should never be run near the reference inputs. avoid crossover of digital and analog signals. traces on opposite sides of the board should run at right angles to each other. this reduces the effects of feedthrough through the board. a microstrip technique is by far the best but not always possible with a double-sided board. in this technique, the component side of the board is dedicated to the ground plane while signal traces are placed on the solder side. it is good practice to use compact, minimum lead length pcb layout design. leads to the input should be as short as possible to minimize ir drops and stray inductance.
ad5520 rev. b | page 20 of 24 typical connection circuit for the ad5520 figure 26 shows the ad5520 as connected in a typical applica- tion. the external components required are three compensation capacitors and six sense resistors, depending on the number of ranges required. if high current ranges >6 ma are required, an external amplifier must be used with relays (or some form of high current switch) to switch in the different current ranges to the dut. other components are also required to make the pmu function. the pmu requires a number of discrete voltage levels: five dac levels for each pmu used in the system, two levels each for the comparator and clamps, and one voltage level for the ad5520 force input voltage. to use the information measured at the dut, an adc such as the ad7665 (a 16-bit adc), must be connected to the measout pin to convert the measured current or voltage to digital for analysis. clldetect measi4h fin bw select compout2 foh1 foh2 foh3 foh0 av ee av cc measi3h clh cll refgnd measiout measout measvout cph cpoh cpol cpl measi5h measil guardin guard measvh measvl agnd qm5 qm4 dgnd dv dd cs standby compout1 compout0 compin2 compin1 compin0 clamp detect i sense inst amp v sense inst amp logics ac0 ac1 clhdetect moe am0 am1 am2 msel fsel cpsel stb cpck ad5520 comparator 125k 12.5k 1.25k 125 12.5 3.126 ad815 relay < 11.5v dut < 100mv 11v measi2h measi1h measi0h +15v ?15v 100pf 1000pf 3000pf foh force amplifier g = 16 g = 1 g = 1 03701-026 figure 26. typical configuration of the ad5520 as used in an ate circuit
ad5520 rev. b | page 21 of 24 typical application circuit figure 27 shows the ad5520 as in an ate system. this device can used as a per pin parametric unit in order to speed up the rate at which testing can be done. it can also be used as a dut power supply, as shown in the application circuit. the central pmu shown in the block diagram ( figure 27 ) is usually a highly accurate pmu and is shared among a number of pins in the tester. in general, many discrete levels are required in an ate system for the pin drivers, comparators, clamps, and active loads. dac devices, such as the ad5379, offer a highly integrated solution for a number of these levels. the ad5379 is a dense 40-channel dac designed with high channel requirements, such as ate. the flexible function of the ad5520 also makes it suited for use in instrumentation applications such as source measure units. source measure units are programmable instruments capable of sourcing and measuring voltage or current simultaneously. the ad5520 provides a more integrated solution in such equipment. central pmu adc dac timing data memory timing generator dll, logic formatter de-skew dac dac dac vterm driver dac dac dac iol vh comp compare memory dac active load dac dac vcom ioh dac vth vtl vcl ppmu adc dac device power supplies adc dac gnd sense guard amp amp 50 coax relays device under test (dut) guard amp vl vch formatter de-skew 03701-027 figure 27. typical application ate circuit
ad5520 rev. b | page 22 of 24 evaluation board for the ad5520 a full-featured evaluation kit is available for the ad5520. it includes an evaluation board with direct hookup via a 36-way centronics connector to a pc. pc-based software to control the ad5520 is also part of the evaluation kit. the evaluation board schematic is shown in figure 28 . note that v dd and v ss must provide sufficient headroom for the force and measure voltage range. in addition to the supply voltages for the evaluation board, it is necessary to provide the voltage levels for the clamp, comparator, and the force input pins (cll, clh, cpl, cph, and fin). smb connections are provided for these voltage inputs. to use the evaluation board, it is also necessary to provide a dut connected via the gold pins. both agnd and dgnd inputs are provided on the board. the agnd and dgnd planes are connected at one location close to the ad5520. it is recommended not to connect agnd and dgnd elsewhere in the system to avoid ground loop problems. refgnd is routed back to agnd at the power block to maintain a clean ground reference for accurate measurements. each supply is decoupled to the relevant ground plane with 10 f and 0.1 f capacitors. the device supply pin is again decoupled with a 10 f and 0.1 f capacitor pair to the relevant ground plane. care should be taken when replacing devices to ensure that the pins line up correctly with the pcb pads.
ad5520 rev. b | page 23 of 24 av cc 27 av cc_g 33 50 standby 22 stb 14 cpck 6 moeb 12 csb 13 am0 21 am1 20 am2 19 fsel 23 cpsel 25 msel 24 ac0 15 ac1 16 cpoh 4 cpol 5 chl-det 8 cll-det 9 qm4 10 qm5 11 compin2 56 compout2 53 compin1 55 compout1 52 compin0 54 compout0 51 dgnd 26 av ee_g 29 av ee_b 48 58 60 61 62 63 64 1 2 59 57 49 47 46 45 44 43 42 41 40 39 38 37 32 31 30 measout measiout measvout fin clh cll cph cpl refgnd refgnd foh measi5h measi4h foh3 measi3h foh2 measi2h foh1 measi1h foh0 measioh measil gaurdin nc guard 36 35 34 measvh nc measvl +15v c3 0.1 f c4 10 f 20v q0 15 16 17 18 19 14 13 12 q1 q2 q3 q4 q5 q6 q7 d0 d1 d2 d3 d4 d5 d6 d7 6 5 4 3 2 7 8 9 c oe 11 1 d0 d1 d2 d3 d4 d5 d6 d7 q0 15 16 17 18 19 14 13 12 q1 q2 q3 q4 q5 q6 q7 d0 d1 d2 d3 d4 d5 d6 d7 6 5 4 3 2 7 8 9 c oe 11 1 d0 d1 d2 d3 d4 d5 d6 d7 q0 15 16 17 18 19 14 13 12 q1 q2 q3 q4 q5 q6 q7 d0 d1 d2 d3 d4 d5 d6 d7 6 5 4 3 2 7 8 9 c oe 11 1 d0 d1 d2 d3 d4 d5 d6 d7 c7, 100pf c8, 1nf c9, 3.3nf c5 0.1 f 20v c6 10 f d[0:7] c26 0.1 f c27 0.1 f c28 0.1 f u2, u3, u4 bypass capacitors +5vd j1?14 j1?1 j1?31 j1?36 j1?6 j1?5 j1?4 j1?3 j1?2 j1?7 j1?8 j1?9 d0 d1 d2 d3 d4 d5 d6 d7 j1?23 j1?22 j1?21 j1?20 j1?19 j1?24 j1?25 j1?26 j1?27 j1?28 j1?29 j1?30 c20 0.1 f c21 10 f +5vd j10?1 j10?2 20v c22 0.1 f c23 10 f j11?1 j11?2 20v c24 0.1 f c25 10 f j11?3 20v 7 17 28 dgnd agnd dv dd dv dd c1 0.1 f c2 10 f 20v 18 3 t4 j2 t5 j3 t6 j4 t7 j5 t8 j6 t9 j7 t10 j8 t11 j9 t12 u5?a ad815arb r12 5k r11 5k relay?g6h rl1 831 9 74210 d1 relay?g6h rl2 831 9 74210 d2 r2, 12.4k r1, 124k c14 r3, 1.24k r4, 124 r5, 12.4 r6 r7 lk1 c17 c18 r10 c19 c15 10pf q1 e c b r8 10k qm4 c16 10pf q1 e c b r9 10k qm5 ?vs +vs c10 10 f 20v c13 10 f 20v ?15v c11 0.1 f c12 0.1 f u5?c ad815arb?24 12 13 +15v t1 t2 t3 14 ad815arb?24 15 16 u5?b 74hct573 74hct573 74hct573 u2 u3 u4 av ee +15v ?15v +5vd +5vd +5vd 03701-028 figure 28. evaluation board schematic
ad5520 preliminary technical data rev. b | page 24 of 24 outline dimensions compliant to jedec standards ms-026-bcd top view (pins down) 1 16 17 33 32 48 49 64 0.27 0.22 0.17 0.50 bsc lead pitch 10.00 bsc sq 12.00 bsc sq pin 1 1.60 max 0.75 0.60 0.45 view a 0.20 0.09 1.45 1.40 1.35 0.08 max coplanarity view a rotated 90 ccw seating plane 0 . 1 5 0 . 0 5 7 3.5 0 figure 29. 64-lead low profile quad flat package [lqfp] (st-64-2) dimensions shown in millimeters ordering guide model temperature range package description package option ad5520jst 0c to 70c 64-lead low profil e quad flat package [lqfp] st-64-2 ad5520jst-reel 0c to 70c 64-lead low profile quad flat package [lqfp] st-64-2 AD5520JSTZ-REEL 1 0c to 70c 64-lead low profile quad flat package [lqfp] st-64-2 eval-ad5520eb evaluation board and software 1 z = pb-free part. ? 2005 analog devices, inc. all rights reserved. trademarks and registered trademarks are the property of their respective owners. c03701-0-9/05(b)

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